Transistors and manufacturing methods thereof

专利摘要:
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor and a method of manufacturing the same, wherein transistors are formed to improve the degree of integration of devices by forming gate electrodes on both sidewalls of trenches formed in a silicon substrate and forming junction regions on the silicon substrate on both sides of the gate electrode. And a method for producing the same.
公开号:KR19980055711A
申请号:KR1019960074947
申请日:1996-12-28
公开日:1998-09-25
发明作者:이영철；김동현
申请人:김영환；현대전자산업 주식회사；
IPC主号:

专利说明:

Transistors and manufacturing methods thereof
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor and a method for manufacturing the same, and more particularly, to a transistor capable of improving the degree of integration of a semiconductor device and a method for manufacturing the same.
In general, a transistor consists of a gate electrode, a source and a drain region. The gate electrode is made of a conductive material such as polysilicon and is electrically separated from the lower silicon substrate by a gate insulating film. The source and drain regions are formed on the silicon substrate at both sides of the gate electrode and include a junction region into which impurity ions are implanted. Then, a conventional transistor manufacturing method will be described with reference to FIGS. 1A and 1B.
Conventionally, as shown in FIG. 1A, a gate insulating film 2 and a polysilicon layer 3 are sequentially formed on a silicon substrate 1, and then the polysilicon layer ( 3) and the gate insulating film 2 are sequentially patterned to form a gate electrode 3A as shown in FIG. 1B. The impurity ions are implanted into the exposed silicon substrate 1 at both sides of the gate electrode 3A to form a junction region 4. However, since the gate electrode 3A of the transistor is patterned by a photolithography process, its width W is determined by the critical dimension of the exposure equipment. Therefore, there is a limit in reducing the width of the gate electrode 3A, and thus it is difficult to manufacture a highly integrated device using the above method.
Accordingly, the present invention provides a transistor and a method for manufacturing the same, which can solve the above-mentioned disadvantages by forming both side gate gate electrodes of a trench formed in a silicon substrate and forming a junction region in the silicon substrate at both sides of the gate electrode. There is a purpose.
According to an aspect of the present invention, a transistor includes a silicon substrate having a trench having a predetermined depth, a gate electrode formed on both sidewalls of the trench, and electrically separated from the silicon substrate by a gate insulating film, And a junction region formed on a silicon substrate at both sides of the gate electrode, and the transistor manufacturing method according to the present invention forms a trench having a predetermined depth in a silicon substrate, and then forms a gate insulating film and a polysilicon on the entire upper surface including the trench. Forming a layer sequentially, forming a gate electrode on both sidewalls of the trench by etching the entire polysilicon layer from the step to the time when the gate insulating layer is exposed, and forming an upper portion of the silicon substrate from the step. And exposed under the trench Group after removing the gate insulating film by implanting the impurity ions into the exposed silicon substrate characterized by comprising the step of forming the bonding region. In addition, the gate electrode is formed in a spacer shape, the gate electrode is characterized in that formed by the depth of the junction region lower than the surface portion of the silicon substrate.
1A and 1B are cross-sectional views of elements for explaining a conventional transistor manufacturing method.
2A to 2D are cross-sectional views of devices for explaining the transistor manufacturing method according to the present invention.
* Description of the symbols for the main parts of the drawings *
1 and 11: silicon substrate 2 and 13: gate insulating film
3 and 14: polysilicon layer 3A and 14B: gate electrode
4 and 15: junction region 12: trench
Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
2A to 2D are cross-sectional views of devices for explaining the method of manufacturing a transistor according to the present invention. FIG. 2A is a cross-sectional view of a trench 12 having a predetermined depth formed on the silicon substrate 11, and FIG. 2B. Is a cross-sectional view of the gate insulating layer 13 and the polysilicon layer 14 sequentially formed on the entire upper surface including the trench 12. The depth of the trench 12 is determined by the width of the gate electrode. In addition, a tungsten silicide layer (not shown) may be further formed on the polysilicon layer 14 to form a gate electrode having a polycide structure.
FIG. 2C illustrates that the polysilicon layer 14 is etched to the entire surface until the gate insulating layer 13 is exposed, thereby forming gate electrodes 14A having spacer shapes on both sidewalls of the trench 12. As a cross-sectional view of the state, the polysilicon layer 14 is etched so that the gate electrode 14A is formed lower than the surface portion of the silicon substrate 11 in consideration of the depth A of the junction region to be formed.
2D illustrates that the junction region 15 is formed by removing impurity ions into the exposed silicon substrate 11 after removing the exposed gate insulating layer 13 above the silicon substrate 11 and the lower portion of the trench 12. As a cross-sectional view of the formed state, a state in which two transistors sharing one junction region 15 is formed is illustrated, and the silicon substrate 11 on both sidewalls of the trench 12 forms a channel region of the transistor. Used as Here, after forming the junction region 15, a tungsten silicide layer may be formed on the gate electrode and the junction region 15.
As described above, according to the present invention, the gate electrodes are formed on both side walls of the trench formed in the silicon substrate, and the junction regions are formed on the silicon substrate on both sides of the gate electrode, thereby reducing the size of the transistor to easily realize high integration of the device. It has an excellent effect.

权利要求:
Claims (8)
[1" claim-type="Currently amended] In a transistor,
A silicon substrate having a trench having a predetermined depth;
Gate electrodes formed on both sidewalls of the trench and electrically separated from the silicon substrate by a gate insulating film;
And a junction region formed on a silicon substrate at both sides of the gate electrode.
[2" claim-type="Currently amended] The method of claim 1,
And the gate electrode is formed of a polyside structure.
[3" claim-type="Currently amended] The method according to claim 1 or 2,
And the gate electrode is formed in a spacer shape.
[4" claim-type="Currently amended] The method according to claim 1 or 2,
And the gate electrode is formed to be lower than the surface portion of the silicon substrate by the depth of the junction region.
[5" claim-type="Currently amended] In the transistor manufacturing method,
Forming a trench of a predetermined depth in the silicon substrate and sequentially forming a gate insulating film and a polysilicon layer on the entire upper surface including the trench;
Forming a gate electrode on both sidewalls of the trench by etching the entire polysilicon layer from the step until the gate insulating layer is exposed;
And removing impurity ions into the exposed silicon substrate after removing the exposed gate insulating layer from the upper portion of the silicon substrate and the lower portion of the trench from the step, thereby forming a junction region.
[6" claim-type="Currently amended] The method of claim 5,
And forming a tungsten silicide layer on the gate electrode and the junction region from the forming of the junction region.
[7" claim-type="Currently amended] The method of claim 5,
The gate electrode is a transistor manufacturing method, characterized in that formed in the shape of a spacer.
[8" claim-type="Currently amended] The method according to claim 5 or 7,
And the gate electrode is formed to be lower than the surface portion of the silicon substrate by the depth of the junction region.

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同族专利:

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引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
1996-12-28|Application filed by 김영환, 현대전자산업 주식회사

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1996-12-28|Priority to KR1019960074947A

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1998-09-25|Publication of KR19980055711A

优先权:

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申请号 | 申请日 | 专利标题

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KR1019960074947A|KR19980055711A|1996-12-28|1996-12-28|Transistors and manufacturing methods thereof|